Many functions of modern devices in automotive, consumer and industrial applications, such as computer technology, mobile communications technology, converting electrical energy and driving an electric motor or an electric machine, rely on semiconductor devices, in particular semiconductor transistors such as field-effect transistors (FETs), for example power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors).
In many applications, vertical MOSFETs with a source metallization and a gate metallization on the front side of the semiconductor substrate, and a drain metallization on the back side of the semiconductor substrate are used. There are, however, applications in which it is desirable for the source metallization of the MOSFET to be located on the front side of its semiconductor substrate whereas the gate metallization and the drain metallization are located on the back side of the semiconductor substrate. Such a device is in the following referred to as source-down MOSFET because the MOSFET can be soldered up-side down with its front side (source metallization is directed downwardly) to a simple lead frame. Thereby, additional costs for a segmented lead frame may be avoided. Furthermore, source-down MOSFETs may particularly efficiently be cooled through the source metallization which is close to the channel region. Further, in application in which the source metallization is during operation at reference potential, typically at ground, no further insulation of the source-down MOSFET may be required. This makes source-down MOSFETs particularly interesting for automotive applications in which the lead frame to which the source metallization of the MOSFET is soldered or glued may simply be mounted or connected to the chassis at ground potential.
For source-down MOSFETs, a conductive via through the semiconductor substrate is typically formed to connect the gate metallization and a gate electrode of the MOSFET. Furthermore, sufficiently reliable electrically insulating regions, for example thermal oxides, are often desired on top and bottom side of the semiconductor substrate, in particular for power semiconductor devices. However, forming of sufficiently reliable insulating thermal oxides typically requires higher temperatures and thus poses limits for the manufacturing. Accordingly, the manufacturing of such devices is often complex and/or expensive. Alternatively, insulated deep vertical trenches may be formed in an early process from the source-side into the wafer to define via regions. Thereafter, the source side may be finished and the wafer thinned at the opposite site, thereby exposing the insulated deep vertical trenches and forming the via regions. This manufacturing method is, however, also expensive. In addition, mechanical stability of the wafer may be weakened when the insulated deep vertical trenches are not completely filled. This may result in wafer breaking during processing.